The present invention relates generally to semiconductor device assemblies that include what are commonly referred to as “multi-chip modules,” in which two or more semiconductor dice are stacked relative to one another. More particularly, the present invention relates to semiconductor device assemblies that include two semiconductor dice stacked together in a face-to-face configuration, laterally extending conductive members providing electrical communication between bond pads on active surfaces of the semiconductor dice and a substrate. The present invention also relates to methods of manufacturing such semiconductor device assemblies.
Integrated circuit semiconductor devices are small electronic circuits formed on or in a surface of a wafer of semiconductor material such as, for example, silicon, gallium arsenide, or other III-V type semiconductor materials. Generally, a plurality of integrated circuit devices is fabricated simultaneously on a single wafer. The wafer is then subdivided into discrete devices (each of which is often referred to as a semiconductor “chip” or “die”), which then may be further processed and “packaged” to provide an end product. Packaging of a semiconductor device typically includes, among other processes, encapsulating at least a portion of the semiconductor die in a dielectric material to electrically insulate and physically protect the relatively fragile semiconductor die. Such semiconductor devices are produced and sold in various package configurations including, for example, lead frame configurations, chip-on-board (COB) configurations, board-on-chip (BOC) configurations, and flip-chip configurations.
The continuing demand for miniaturization of high performance electronic devices (such as cell phones, portable computers, and other hand-held devices) has required that integrated circuit semiconductor devices be as small as possible and consume as little surface area as possible on the circuit boards or other substrates on which they are mounted.
In an effort to conserve the amount of surface area occupied by integrated circuit devices on a substrate, various types of increased density packages have been developed. Among these semiconductor device packages are the so-called multi-chip modules (MCM), which may include assemblies of semiconductor devices that are stacked one on top of another. The amount of surface area on a carrier substrate that may be saved by stacking semiconductor devices is readily apparent—a stack of semiconductor devices consumes roughly the same surface area on a carrier substrate as a single, horizontally oriented semiconductor device or semiconductor device package.
Multi-chip modules may contain a number of semiconductor devices that perform the same or different functions, effectively combining the functionality of all of the semiconductor devices thereof into a single package.
A multi-chip module 10 is shown in FIG. 1A. The multi-chip module 10 is configured as a chip-on-board (COB) type semiconductor package, in which a first semiconductor die 12 having an active surface 14 and a back side 15 is mounted on a substrate 22 such that the active surface 14 faces upward and the back side 15 is disposed adjacent and attached to the substrate 22 by way of an adhesive material 24.
The multi-chip module 10 also includes a second semiconductor die 16 having an active surface 18 and a back side 19. The second semiconductor die 16 is mounted to and positioned vertically above the first semiconductor die 12 such that the active surface 18 faces upward and the back side 19 is disposed adjacent and attached to the first semiconductor die 12 by way of an adhesive material 24.
The first semiconductor die 12 may include a plurality of electrically conductive bond pads 28 disposed on the active surface 14 thereof, and the second semiconductor die 16 may include a plurality of electrically conductive bond pads 28′ disposed on the active surface 18 thereof. The conductive bond pads 28, 28′ may electrically communicate with the integrated circuits contained within each of the respective semiconductor dice 12, 16. As shown in FIG. 1B, the bond pads 28, 28′ may be disposed in one or more rows extending substantially along or proximate to a centerline 21 of each of the first semiconductor die 12 and the second semiconductor die 16.
Laterally extending conductive elements 26 such as bond wires are used to provide electrical communication between conductive bond pads 28 on the active surface 14 of the first semiconductor die 12 and conductive terminals 30 on a first surface of the substrate 22, and between conductive bond pads 28′ on the active surface 18 of the second semiconductor die 16 and the conductive terminals 30 on the first surface of the substrate 22. The multi-chip module 10 may also include an encapsulating material 36 that is used to protect and insulate the first semiconductor die 12, the second semiconductor die 16, and the laterally extending conductive elements 26.
Horizontally extending conductive traces and vertically extending conductive vias may be used to provide electrical communication between the conductive terminals 30 and conductive terminals 32 provided on a second, opposite surface of the substrate 22. Conductive solder bumps 34 may be provided on the conductive terminals 32 and used to structurally and electrically couple the multi-chip module 10 to a higher-level substrate such as a circuit board.
Another multi-chip module 38 is shown in FIG. 2. The multi-chip module 38 is configured as a board-on-chip (BOC) type semiconductor package, in which a first semiconductor die 12 having an active surface 14 and a back side 15 is mounted on a substrate 40 such that the active surface 14 faces downward and is disposed adjacent and attached to the substrate 40 by way of an adhesive material 24.
The substrate 40 shown in FIG. 2 is substantially similar to the substrate 22 shown in FIG. 1A. The substrate 40, however, also includes an aperture 42 through which the plurality of bond pads 28 disposed on the active surface 14 of the first semiconductor die 12 are exposed. Laterally extending conductive elements 26 such as bond wires that extend through the aperture 42 are used to provide electrical communication between the bond pads 28 disposed on the active surface 14 of the first semiconductor die 12 and conductive terminals or traces on the second side of the substrate 40 opposite the semiconductor die 12.
The multi-chip module 38 also includes a second semiconductor die 16 having an active surface 18 and a back side 19. The second semiconductor die 16 is mounted to and positioned vertically above the first semiconductor die 12 such that the active surface 18 faces upward and the back side 19 is disposed adjacent and attached to the back side 15 of the first semiconductor die 12 by way of an adhesive material 24. Laterally extending conductive elements 26 such as bond wires are used to provide electrical communication between the bond pads 28′ disposed on the active surface 18 of the second semiconductor die 16 and conductive terminals 30 on the substrate 40. As previously discussed in relation to FIG. 1B, the bond pads 28 of the first semiconductor die 12 and the bond pads 28′ of the second semiconductor die 16 may be disposed in one or more rows extending substantially along or proximate to a centerline 21 of each of the first semiconductor die 12 and the second semiconductor die 16.
The multi-chip module 38 may also include an encapsulating material 36 that is used to protect and insulate the first semiconductor die 12, the second semiconductor die 16, and the laterally extending conductive elements 26.
Horizontally extending conductive traces and vertically extending conductive vias may be used to provide electrical communication between the conductive terminals 30 and conductive terminals 32 provided on a second, opposite surface of the substrate 22. Conductive solder bumps 34 may be provided on the conductive terminals 32 and used to structurally and electrically couple the multi-chip module 38 to a higher-level substrate such as a circuit board.
A large number of manufacturing processes or steps are required to fabricate the devices shown in FIGS. 1A and 1B and FIG. 2, each of which contributes to the cost of the device.
There is a need for multi-chip modules that require fewer manufacturing processes for fabrication thereof, include fewer components, exhibit improved electrical performance, and that are smaller than multi-chip modules presently known in the art.